Integrated circuits (ICs), particularly integrated circuits formed of MOS transistors, are generally vulnerable to damage from electrostatic discharge (ESD), such as high voltage transients in electrical equipment. In some equipment, high voltage transients may have positive and/or negative peak levels of 100 volts or more and may have a duration of several microseconds. High voltage electrostatic discharge (ESD) transients can also result from a user becoming electrostatically charged, for example, by friction or by induction and touching equipment controls.
SCRs have been used, both parasitically and deliberately, to protect ICs; see for example, U.S. Pat. Nos. 4,400,711, 4,405,933, 4,631,567 and 4,692,781. The major advantage of these SCR protection structures is their high energy absorbing capability. However, unless special precautions are taken, they have two major disadvantages. One such disadvantage is that they have a relatively high trigger voltage. This becomes increasingly serious as IC geometries shrink below the 0.8 micrometer (.mu.m) level. This is because the gate oxide failure voltage is close to the lowest junction breakdown voltage. This results from the fact that junction breakdowns have, of necessity, remained high, while gate oxide thickness, and hence breakdown voltage, has scaled down with device geometries. At the 0.8 .mu.m level, worst case oxide breakdowns are in the 10-12 volt range, and "naturally triggered" SCRs require about a 20-25 volt transient.
Another disadvantage of SCRs is their tendency to remain "on" after the transient is finished. This occurs when the SCR is triggered in an operating system. If the circuit connections to the SCR are capable of supplying a current in excess of the holding current for the SCR, it remains in a conductive, clamped state when the transient is finished. If the protection SCR is used for input/output (I/O) protection on an application specific IC (ASIC) with a known external interface, it is often possible to design the SCR to have a high holding current which exceeds the internal/external current source capability. However, if the SCR is intended to protect the IC power supply pins against the effects of ESD, triggering the protection SCR in an operating circuit may have catastrophic results. The IC could be destroyed as happened with some early CMOS circuits were when a parasitic SCR was triggered.
Therefore for an SCR to operate properly as a protection device, it would be desirable to have an SCR which has a trigger voltage only a few volts above the maximum supply voltage, and a clamping voltage which is only just above (0.5 v to 1.0 v) the maximum supply voltage. Such a device would trigger quickly into its plasma state, but turn off when the transient was finished, even if the device was protecting the power supply pins.